Urmăriți
Grace Zgheib
Grace Zgheib
Processor Architecture Lab, EPFL
Adresă de e-mail confirmată pe epfl.ch
Titlu
Citat de
Citat de
Anul
Architectural enhancements in intel® agilex™ fpgas
J Chromczak, M Wheeler, C Chiasson, D How, M Langhammer, ...
Proceedings of the 2020 ACM/SIGDA International Symposium on Field …, 2020
472020
Revisiting and-inverter cones
G Zgheib, L Yang, Z Huang, D Novo, H Parandeh-Afshar, H Yang, ...
Proceedings of the 2014 ACM/SIGDA international symposium on Field …, 2014
372014
FPRESSO: Enabling express transistor-level exploration of FPGA architectures
G Zgheib, M Lortkipanidze, M Owaida, D Novo, P Ienne
Proceedings of the 2016 ACM/SIGDA International Symposium on Field …, 2016
202016
Evaluating FPGA clusters under wide ranges of design parameters
G Zgheib, P Ienne
2017 27th International Conference on Field Programmable Logic and …, 2017
182017
Shadow and-inverter cones
H Parandeh-Afshar, G Zgheib, D Novo, M Purnaprajna, P Ienne
2013 23rd International Conference on Field programmable Logic and …, 2013
162013
NAND-NOR: A compact, fast, and delay balanced FPGA logic element
Z Huang, X Wei, G Zgheib, W Li, Y Lin, Z Jiang, K Tu, P Ienne, H Yang
Proceedings of the 2017 ACM/SIGDA International Symposium on Field …, 2017
112017
Straight to the point: Intra-and intercluster LUT connections to mitigate the delay of programmable routing
S Nikolić, G Zgheib, P Ienne
Proceedings of the 2020 ACM/SIGDA International Symposium on Field …, 2020
82020
Automatic wire modeling to explore novel FPGA architectures
G Zgheib, P Ienne
2016 International Conference on Field-Programmable Technology (FPT), 181-184, 2016
82016
Improving circuit mapping performance through mig-based synthesis for carry chains
Z Chu, X Tang, M Soeken, A Petkovska, G Zgheib, L Amarù, Y Xia, ...
Proceedings of the on Great Lakes Symposium on VLSI 2017, 131-136, 2017
72017
Reducing the pressure on routing resources of FPGAs with generic logic chains
H Parandeh-Afshar, G Zgheib, P Brisk, P Ienne
Proceedings of the 19th ACM/SIGDA international symposium on Field …, 2011
72011
Detailed placement for dedicated lut-level FPGA interconnect
S Nikolić, G Zgheib, P Ienne
ACM Transactions on Reconfigurable Technology and Systems 15 (4), 1-33, 2022
52022
Improved carry chain mapping for the VTR flow
A Petkovska, G Zgheib, D Novo, M Owaida, A Mishchenko, P Ienne
2015 International Conference on Field Programmable Technology (FPT), 80-87, 2015
52015
A technology mapper for depth-constrained FPGA logic cells
Z Jiang, G Zgheib, CY Lin, D Novo, Z Huang, L Yang, H Yang, P Ienne
2015 25th International Conference on Field Programmable Logic and …, 2015
52015
Enhanced Technology Mapping for FPGAs with Exploration of Cell Configurations
G Zgheib, I Ouaiss
Journal of Circuits, Systems, and Computers 24 (3), 2015
42015
Shadow AICs: Reaping the benefits of And-Inverter Cones with minimal architectural impact
H Parandeh-Afshar, G Zgheib, D Novo, M Purnaprajna, P Ienne
Proceedings of the ACM/SIGDA international symposium on Field programmable …, 2013
42013
Routing wire optimization through generic synthesis on FPGA carry chains
H Parandeh-Afshar, G Zgheib, P Brisk, P Ienne
eScholarship, University of California, 2011
42011
Timing-driven placement for FPGA architectures with dedicated routing paths
S Nikolić, G Zgheib, P Ienne
2020 30th International Conference on Field-Programmable Logic and …, 2020
22020
Finding a needle in the haystack of hardened interconnect patterns
S Nikolic, G Zgheib, P Ienne
2019 29th International Conference on Field Programmable Logic and …, 2019
22019
Leading the Blind: Automated Transistor-Level Modeling for FPGA Architects
G Zgheib
EPFL, 2017
22017
An ant colony optimization heuristic to optimize prediction of stability of object-oriented components
H Harmanani, D Azar, G Zgheib, D Kozhaya
2015 IEEE International Conference on Information Reuse and Integration, 225-228, 2015
22015
Sistemul nu poate realiza operația în acest moment. Încercați din nou mai târziu.
Articole 1–20