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Domenik Helms
Domenik Helms
Principal Scientist, OFFIS e.V.
Adresă de e-mail confirmată pe offis.de - Pagina de pornire
Titlu
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Predictable design of low power systems by pre-implementation estimation and optimization
W Nebel, A Stammermann, D Helms, E Schmidt, M Schulte, L Kruse, ...
US Patent 7,725,848, 2010
952010
Binding allocation and floorplanning in low power high-level synthesis
A Stammermann, D Helms, M Schulte, A Schulz, W Nebel
ICCAD-2003. International Conference on Computer Aided Design (IEEE Cat. No …, 2003
732003
Leakage in CMOS circuits–an introduction
D Helms, E Schmidt, W Nebel
International Workshop on Power and Timing Modeling, Optimization and …, 2004
712004
Leakage models for high level power estimation
D Helms
Universität Oldenburg, 2009
28*2009
An embedded CNN implementation for on-device ECG analysis
A Burger, C Qian, G Schiele, D Helms
2020 IEEE International Conference on Pervasive Computing and Communications …, 2020
252020
Behavioral-level thermal-and aging-estimation flow
S Rosinger, M Metzdorf, D Helms, W Nebel
2011 12th Latin American Test Workshop (LATW), 1-6, 2011
162011
Modelling the impact of high level leakage optimization techniques on the delay of RT-components
M Hoyer, D Helms, W Nebel
International Workshop on Power and Timing Modeling, Optimization and …, 2007
162007
Analysis and modeling of subthreshold leakage of RT-components under PTV and state variation
D Helms, G Ehmen, W Nebel
Proceedings of the 2006 international symposium on Low power electronics and …, 2006
162006
Accurate PTV, state, and ABB aware RTL blackbox modeling of subthreshold, gate, and PN-junction leakage
D Helms, M Hoyer, W Nebel
International Workshop on Power and Timing Modeling, Optimization and …, 2006
162006
An improved power macro-model for arithmetic datapath components
D Helms, E Schmidt, A Schulz, A Stammermann, W Nebel
International Workshop on Power and Timing Modeling, Optimization and …, 2002
152002
RT level timing modeling for aging prediction
N Koppaetzky, M Metzdorf, R Eilers, D Helms, W Nebel
2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 297-300, 2016
142016
Voltage-and ABB-island optimization in high level synthesis
D Helms, O Meyer, M Hoyer, W Nebel
Proceedings of the 2007 international symposium on Low power electronics and …, 2007
132007
Efficient NBTI modeling technique considering recovery effects
R Eilers, M Metzdorf, D Helms, W Nebel
Proceedings of the 2014 international symposium on Low power electronics and …, 2014
122014
RTL power modeling and estimation of sleep transistor based power gating
S Rosinger, D Helms, W Nebel
International Workshop on Power and Timing Modeling, Optimization and …, 2007
122007
High-level power estimation and analysis
W Nebel
Low-Power CMOS Circuits, 18-1-18-24, 2018
112018
Considering variation and aging in a full chip design methodology at system level
D Helms, K Grüttner, R Eilers, M Metzdorf, K Hylla, F Poppen, W Nebel
Proceedings of the 2014 Electronic System Level Synthesis Conference (ESLsyn …, 2014
92014
Interconnect driven low power high-level synthesis
A Stammermann, D Helms, M Schulte, A Schulz, W Nebel
International Workshop on Power and Timing Modeling, Optimization and …, 2003
82003
TCAD-based characterization of logic cells: Power, performance, area, and variability
HW Karner, C Kernstock, Z Stanojević, O Baumgartner, F Schanovsky, ...
2017 International Symposium on VLSI Technology, Systems and Application …, 2017
72017
Analysis of NBTI effects on high frequency digital circuits
A Unutulmaz, D Helms, R Eilers, M Metzdorf, B Kaczer, W Nebel
2016 Design, Automation & Test in Europe Conference & Exhibition (DATE), 223-228, 2016
72016
Accelerating and pruning cnns for semantic segmentation on fpga
P Morì, MR Vemparala, N Fasfous, S Mitra, S Sarkar, A Frickenstein, ...
Proceedings of the 59th ACM/IEEE Design Automation Conference, 145-150, 2022
62022
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