Micromachined high-Q inductors in a 0.18-/spl mu/m copper interconnect low-k dielectric CMOS process H Lakdawala, X Zhu, H Luo, S Santhanam, LR Carley, GK Fedder IEEE Journal of Solid-State Circuits 37 (3), 394-403, 2002 | 216* | 2002 |
A 1.1 v 50mw 2.5 gs/s 7b time-interleaved c-2c sar adc in 45nm lp digital cmos E Alpman, H Lakdawala, LR Carley, K Soumyanath 2009 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2009 | 193 | 2009 |
A 28mW spectrum-sensing reconfigurable 20MHz 72dB-SNR 70dB-SNDR DT ΔΣ ADC for 802.11 n/WiMAX receivers P Malla, H Lakdawala, K Kornegay, K Soumyanath 2008 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2008 | 135 | 2008 |
A class-E PA with pulse-width and pulse-position modulation in 65 nm CMOS JS Walling, H Lakdawala, Y Palaskas, A Ravi, O Degani, K Soumyanath, ... IEEE Journal of Solid-State Circuits 44 (6), 1668-1678, 2009 | 131 | 2009 |
RF CMOS technology scaling in high-k/metal gate era for RF SoC (system-on-chip) applications CH Jan, M Agostinelli, H Deshpande, MA El-Tanani, W Hafez, U Jalan, ... 2010 international electron devices meeting, 27.2. 1-27.2. 4, 2010 | 119 | 2010 |
A 2.4-GHz 20–40-MHz channel WLAN digital outphasing transmitter utilizing a delay-based wideband phase modulator in 32-nm CMOS A Ravi, P Madoglio, H Xu, K Chandrashekar, M Verhelst, S Pellerano, ... IEEE Journal of Solid-State Circuits 47 (12), 3184-3196, 2012 | 109 | 2012 |
A transformer-combined 31.5 dBm outphasing power amplifier in 45 nm LP CMOS with dynamic power control for back-off power efficiency enhancement W Tai, H Xu, A Ravi, H Lakdawala, O Bochobza-Degani, LR Carley, ... IEEE Journal of Solid-State Circuits 47 (7), 1646-1658, 2012 | 92 | 2012 |
A 1.05 V 1.6 mW, 0.45 (°) C 3\sigma Resolution\Sigma\Delta Based Temperature Sensor With Parasitic Resistance Compensation in 32 nm Digital CMOS Process H Lakdawala, YW Li, A Raychowdhury, G Taylor, K Soumyanath IEEE Journal of Solid-State Circuits 44 (12), 3621-3630, 2009 | 81 | 2009 |
A 1.05 V 1.6 mW 0.45° C 3σ-resolution ΔΣ-based temperature sensor with parasitic-resistance compensation in 32nm CMOS YW Li, H Lakdawala, A Raychowdhury, G Taylor, K Soumyanath 2009 IEEE International Solid-State Circuits Conference-Digest of Technical …, 2009 | 72 | 2009 |
A 5-GHz 20-dBm power amplifier with digitally assisted AM-PM correction in a 90-nm CMOS process Y Palaskas, SS Taylor, S Pellerano, I Rippke, R Bishop, A Ravi, ... IEEE journal of solid-state circuits 41 (8), 1757-1763, 2006 | 71 | 2006 |
A 20dBm 2.4 GHz digital outphasing transmitter for WLAN application in 32nm CMOS P Madoglio, A Ravi, H Xu, K Chandrashekar, M Verhelst, S Pellerano, ... 2012 IEEE International Solid-State Circuits Conference, 168-170, 2012 | 61 | 2012 |
Temperature stabilization of CMOS capacitive accelerometers H Lakdawala, GK Fedder Journal of Micromechanics and Microengineering 14 (4), 559, 2004 | 60 | 2004 |
A copper CMOS-MEMS z-axis gyroscope H Luo, X Zhu, H Lakdawala, LR Carley, GK Fedder Technical Digest. MEMS 2002 IEEE International Conference. Fifteenth IEEE …, 2002 | 60 | 2002 |
Analog/mixed-signal design challenges in 7-nm CMOS and beyond ALS Loke, D Yang, TT Wee, JL Holland, P Isakanian, K Rim, S Yang, ... 2018 IEEE Custom Integrated Circuits Conference (CICC), 1-8, 2018 | 50 | 2018 |
A 1.2 V 2.64 GS/s 8 bit 39 mW skew-tolerant time-interleaved SAR ADC in 40 nm digital LP CMOS for 60 GHz WLAN S Kundu, E Alpman, JHL Lu, H Lakdawala, J Paramesh, B Jung, S Zur, ... IEEE Transactions on Circuits and Systems I: Regular Papers 62 (8), 1929-1939, 2015 | 47 | 2015 |
A 32nm low power RF CMOS SOC technology featuring high-k/metal gate P VanDerVoorn, M Agostinelli, SJ Choi, G Curello, H Deshpande, ... 2010 Symposium on VLSI Technology, 137-138, 2010 | 47 | 2010 |
Analysis of temperature-dependent residual stress gradients in CMOS micromachined structures H Lakdawala, GK Fedder Transducers 99, 526-529, 1999 | 43 | 1999 |
A 630μW zero-crossing-based ΔΣ ADC using switched-resistor current sources in 45nm CMOS T Musah, S Kwon, H Lakdawala, K Soumyanath, UK Moon 2009 IEEE Custom Integrated Circuits Conference, 1-4, 2009 | 42 | 2009 |
A 0.8–2 GHz Fully-Integrated QPLL-Timed Direct-RF-Sampling BandpassADC in 0.13m CMOS S Gupta, D Gangopadhyay, H Lakdawala, JC Rudell, DJ Allstot IEEE Journal of Solid-State Circuits 47 (5), 1141-1153, 2012 | 41 | 2012 |
A 2.5GHz 32nm 0.35mm23.5dB NF −5dBm P1dBfully differential CMOS push-pull LNA with integrated 34dBm T/R switch and ESD protection CT Fu, H Lakdawala, SS Taylor, K Soumyanath 2011 IEEE International Solid-State Circuits Conference, 56-58, 2011 | 40 | 2011 |