| 276-Pin buffered memory module with enhanced fault tolerance DM Dreps, FD Ferriaolo, KC Gower, MW Kellogg, RA Rippens US Patent 7,224,595, 2007 | 196 | 2007 |
| Smart memory interface PW Coteus, DM Dreps, F Ferraiolo US Patent 6,292,903, 2001 | 178 | 2001 |
| 5.1 POWER8TM: A 12-core server-class processor in 22nm SOI with 7.6Tb/s off-chip bandwidth EJ Fluhr, J Friedrich, D Dreps, V Zyuban, G Still, C Gonzalez, A Hall, ... 2014 IEEE International Solid-State Circuits Conference Digest of Technical …, 2014 | 120 | 2014 |
| Advanced memory device having improved performance, reduced power and increased reliability K Kim, GL Chiu, PW Coteus, DM Dreps, KC Gower, HC Hunter, CA Kilmer, ... US Patent 8,307,270, 2012 | 116 | 2012 |
| On-chip voltage controlled oscillator DM Dreps, RP Rizzo US Patent 5,604,466, 1997 | 108 | 1997 |
| Self-healing chip-to-chip interface WD Becker, DM Dreps, FD Ferraiolo, A Haridass, RJ Reese US Patent 7,362,697, 2008 | 104 | 2008 |
| A 2.6 mW/Gbps 12.5 Gbps RX with 8-tap switched-capacitor DFE in 32 nm CMOS T Toifl, C Menolfi, M Ruegg, R Reutemann, D Dreps, T Beukema, A Prati, ... IEEE Journal of Solid-State Circuits 47 (4), 897-910, 2012 | 86 | 2012 |
| Advanced memory device having reduced power and improved performance PW Coteus, DM Dreps, KC Gower, HC Hunter, CA Kilmer, K Kim, ... US Patent 7,948,817, 2011 | 81 | 2011 |
| Controlling for variable impedance and voltage in a memory system DM Dreps, DJ Chen, WF Lawson, DW Mann US Patent 7,710,144, 2010 | 71 | 2010 |
| Cascaded differential receiver circuit DR Cecchi, DM Dreps US Patent 6,549,971, 2003 | 68 | 2003 |
| POWER7™, a highly parallel, scalable multi-core high end server processor DF Wendel, R Kalla, J Warnock, R Cargnoni, SG Chu, JG Clabes, ... IEEE Journal of Solid-State Circuits 46 (1), 145-161, 2010 | 66 | 2010 |
| The 12-core power8™ processor with 7.6 tb/s io bandwidth, integrated voltage regulation, and resonant clocking EJ Fluhr, S Baumgartner, D Boerstler, JF Bulzacchelli, T Diemoz, D Dreps, ... IEEE Journal of Solid-State Circuits 50 (1), 10-23, 2014 | 62 | 2014 |
| IBM POWER9 opens up a new era of acceleration enablement: OpenCAPI J Stuecheli, WJ Starke, JD Irish, LB Arimilli, D Dreps, B Blaner, ... IBM Journal of Research and Development 62 (4/5), 8: 1-8: 8, 2018 | 60 | 2018 |
| Dynamic wave-pipelined interface apparatus and methods therefor DM Dreps, FD Ferraiolo, KC Gower US Patent 6,654,897, 2003 | 56 | 2003 |
| CMOS high-speed differential to single-ended converter circuit DW Boerstler, DM Dreps US Patent 5,821,809, 1998 | 55 | 1998 |
| Pseudo-differential parallel source synchronous bus D Dreps, R Williams US Patent App. 09/821,065, 2002 | 49 | 2002 |
| A 4.5 mW/Gb/s 6.4 Gb/s 22+ 1-lane source synchronous receiver core with optional cleanup PLL in 65 nm CMOS R Reutemann, M Ruegg, F Keyser, J Bergkvist, D Dreps, T Toifl, ... IEEE Journal of solid-state circuits 45 (12), 2850-2860, 2010 | 48 | 2010 |
| 2.1 summit and sierra: Designing ai/hpc supercomputers. In 2019 IEEE International Solid-State Circuits Conference-(ISSCC) JA Kahle, J Moreno, D Dreps IEEE, 42¶43, 2019 | 44 | 2019 |
| 4.1 22nm next-generation ibm system z microprocessor J Warnock, B Curran, J Badar, G Fredeman, D Plass, Y Chan, S Carey, ... 2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of …, 2015 | 44 | 2015 |
| Method and apparatus for testing, characterizing and tuning a chip interface SM Douskey, DM Dreps, FD Ferraiolo, CW Preuss, RJ Reese, PW Rudrud, ... US Patent 6,735,543, 2004 | 43 | 2004 |
