Heechun Park

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Sung Kyu LimProfessor, Georgia Institute of TechnologyAdresă de e-mail confirmată pe ece.gatech.edu
Taewhan KimSeoul National University, Department of Electrical and Computer EngineeringAdresă de e-mail confirmată pe ssl.snu.ac.kr
Saibal MukhopadhyayProfessor of Electrical Engineering, Georgia Institute of TechnologyAdresă de e-mail confirmată pe ece.gatech.edu
Jinwoo KimGeorgia Institute of TechnologyAdresă de e-mail confirmată pe gatech.edu
Madhavan SwaminathanDept Head EE; William E. Leonhard Endowed Chair; Director CHIMES (an SRC JUMP 2.0 Center) Penn StateAdresă de e-mail confirmată pe psu.edu
Gauthaman MuraliGeorgia Institute of TechnologyAdresă de e-mail confirmată pe gatech.edu
Hakki M. TorunApple Inc.Adresă de e-mail confirmată pe apple.com
Bon Woong KuGeorgia Institute of TechnologyAdresă de e-mail confirmată pe gatech.edu
Venkata Chaitanya Krishna ChekuriApple Inc.Adresă de e-mail confirmată pe apple.com
Tushar KrishnaAssociate Professor, Georgia TechAdresă de e-mail confirmată pe ece.gatech.edu
Eric QinGeorgia TechAdresă de e-mail confirmată pe gatech.edu
Krishnendu ChakrabartyFulton Professor of Microelectronics, School of Electrical and Computer and Energy EngineeringAdresă de e-mail confirmată pe asu.edu
Arjun ChaudhuriNVIDIAAdresă de e-mail confirmată pe nvidia.com
Sanmitra BanerjeeSr. DFX Methodology Engineer, NVIDIAAdresă de e-mail confirmată pe nvidia.com
Arvind SinghRambus Cryptography ResearchAdresă de e-mail confirmată pe rambus.com
Minah LeeGeorgia Institute of TechnologyAdresă de e-mail confirmată pe gatech.edu
Hyoukjun KwonAssistant Professor, University of California, IrvineAdresă de e-mail confirmată pe uci.edu
Kallol RoyAssistant Professor, University of Tartu, EstoniaAdresă de e-mail confirmată pe ut.ee
Nihar DasariGraduate Student, Georgia Institute of TechnologyAdresă de e-mail confirmată pe gatech.edu
Kyungwook ChangSungkyunkwan UniversityAdresă de e-mail confirmată pe skku.edu

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Heechun Park

Assistant Professor, UNIST

Adresă de e-mail confirmată pe unist.ac.kr - Pagina de pornire

Electronic Design Automation Computer-Aided Design 3D IC 2.5D IC Machine Learning for EDA


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Architecture, chip, and package co-design flow for 2.5 D IC design enabling heterogeneous IP reuse J Kim, G Murali, H Park, E Qin, H Kwon, VCK Chekuri, N Dasari, A Singh, ... 2019 56th ACM/IEEE Design Automation Conference (DAC), 1-6, 2019	49	2019
Architecture, chip, and package codesign flow for interposer-based 2.5-D chiplet integration enabling heterogeneous IP reuse J Kim, G Murali, H Park, E Qin, H Kwon, VCK Chekuri, NM Rahman, ... IEEE Transactions on Very Large Scale Integration (VLSI) Systems 28 (11 …, 2020	47	2020
Physical Design for 3D Integrated Circuits - Design Methodology for TSV-Based 3D Clock Networks (Chapter 7) H Park, T Kim CRC Press, 2016	21*	2016
Pseudo-3D approaches for commercial-grade RTL-to-GDS tool flow targeting monolithic 3D ICs H Park, BW Ku, K Chang, DE Shim, SK Lim Proceedings of the 2020 International Symposium on Physical Design, 47-54, 2020	19	2020
Synthesis of TSV fault-tolerant 3-D clock trees H Park, T Kim IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2014	17	2014
Design flow for active interposer-based 2.5-D ICs and study of RISC-V architecture with secure NoC H Park, J Kim, VCK Chekuri, MA Dolatsara, M Nabeel, A Bojesomo, ... IEEE Transactions on Components, Packaging and Manufacturing Technology 10 …, 2020	13	2020
Built-in self-test for inter-layer vias in monolithic 3D ICs A Chaudhuri, S Banerjee, H Park, BW Ku, K Chakrabarty, SK Lim 2019 IEEE European Test Symposium (ETS), 1-6, 2019	13	2019
RTL-to-GDS tool flow and design-for-test solutions for monolithic 3D ICs H Park, K Chang, BW Ku, J Kim, E Lee, D Kim, A Chaudhuri, S Banerjee, ... Proceedings of the 56th Annual Design Automation Conference 2019, 1-4, 2019	10	2019
Advances in design and test of monolithic 3-D ICs A Chaudhuri, S Banerjee, H Park, J Kim, G Murali, E Lee, D Kim, SK Lim, ... IEEE Design & Test 37 (4), 92-100, 2020	8	2020
Built-in self-test and fault localization for inter-layer vias in monolithic 3D ICs A Chaudhuri, S Banerjee, J Kim, H Park, BW Ku, S Kannan, ... ACM Journal on Emerging Technologies in Computing Systems (JETC) 18 (1), 1-37, 2021	6	2021
Structure optimizations of neuromorphic computing architectures for deep neural network H Park, T Kim 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 183-188, 2018	6	2018
Pseudo-3D Physical Design Flow for Monolithic 3D ICs: Comparisons and Enhancements H Park, BW Ku, K Chang, DE Shim, SK Lim ACM Transactions on Design Automation of Electronic Systems (TODAES) 26 (5 …, 2021	5	2021
Synthesizing asynchronous circuits toward practical use H Park, T Kim 2016 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 47-52, 2016	5	2016
Comprehensive technique for designing and synthesizing TSV fault-tolerant 3D clock trees H Park, T Kim 2013 IEEE/ACM International Conference on Computer-Aided Design (ICCAD), 691-696, 2013	4	2013
DTOC: integrating Deep-learning driven Timing Optimization into the state-of-the-art Commercial EDA tool K Chang, J Ahn, H Park, KM Choi, T Kim 2023 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2023	3	2023
A systematic removal of minimum implant area violations under timing constraint E Jeong, H Park, T Kim 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE), 933-938, 2022	3	2022
Integrated circuit having main route and detour route for signal transmission and integrated circuit package including the same LIM Kyounghwan, HS Park, KS Kim, LEE Bonghyun, RIM Chul, ... US Patent 9,524,922, 2016	3	2016
Design Space Exploration of Power Delivery in Heterogeneous Integration HM Torun, N Dasari, A Singh, M Lee, J Kim, H Park, HJ Kwon, E Qin, ... Government Microcircuit Application and Critical Technology Conference …, 2019	2	2019
Tightly Linking 3D Via Allocation Towards Routing Optimization for Monolithic 3D ICs S Kim, S Chung, T Kim, H Park Proceedings of the ACM/IEEE International Symposium on Low Power Electronics …, 2022	1	2022
Speeding-up neuromorphic computation for neural networks: Structure optimization approach H Park, T Kim Integration 82, 104-114, 2022	1	2022

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