Ian O'Connor
Cited by
Cited by
System level assessment of an optical NoC in an MPSoC platform
M Briere, B Girodias, Y Bouchebaba, G Nicolescu, F Mieyeville, F Gaffiot, ...
2007 Design, Automation & Test in Europe Conference & Exhibition, 1-6, 2007
CNTFET modeling and reconfigurable logic-circuit design
I O'Connor, J Liu, F Gaffiot, F Prégaldiny, C Lallement, C Maneux, ...
IEEE Transactions on Circuits and Systems I: Regular Papers 54 (11), 2365-2379, 2007
Can we go towards true 3-D architectures?
PE Gaillardon, H Ben-Jamaa, PH Morel, JP Noël, F Clermidy, I O'Connor
Proceedings of the 48th Design Automation Conference, 282-283, 2011
ULPFA: A new efficient design of a power-aware full adder
I Hassoune, D Flandre, I O'Connor, JD Legat
IEEE Transactions on Circuits and Systems I: Regular Papers 57 (8), 2066-2074, 2008
Optical ring network-on-chip (ORNoC): Architecture and design methodology
S Le Beux, J Trajkovic, I O'Connor, G Nicolescu, G Bois, P Paulin
2011 Design, Automation & Test in Europe, 1-6, 2011
Optical solutions for system-level interconnect
I O'Connor
Proceedings of the 2004 international workshop on System level interconnect …, 2004
Computing with ferroelectric FETs: Devices, models, systems, and applications
A Aziz, ET Breyer, A Chen, X Chen, S Datta, SK Gupta, M Hoffmann, ...
2018 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2018
Chameleon: Channel efficient optical network-on-chip
S Le Beux, H Li, I O'Connor, K Cheshmi, X Liu, J Trajkovic, G Nicolescu
2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2014
Design and architectural assessment of 3-D resistive memory technologies in FPGAs
PE Gaillardon, D Sacchetto, GB Beneventi, MHB Jamaa, L Perniola, ...
IEEE Transactions on Nanotechnology 12 (1), 40-50, 2012
On-chip optical interconnect for low-power
I O’Connor, F Gaffiot
Ultra Low-Power Electronics and Design, 21-39, 2004
Heterogeneous modelling of an optical network-on-chip with SystemC
M Briere, E Drouard, F Mieyeville, D Navarro, I O'Connor, F Gaffiot
16th IEEE International Workshop on Rapid System Prototyping (RSP'05), 10-16, 2005
Reduction methods for adapting optical network on chip topologies to specific routing applications
I O’Connor, F Mieyeville, F Gaffiot, A Scandurra, G Nicolescu
Proceedings of DCIS, 2008
Systematic simulation-based predictive synthesis of integrated optical interconnect
I O'Connor, F Tissafi-Drissi, F Gaffiot, J Dambre, M De Wilde, ...
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 15 (8), 927-940, 2007
Power dissipation in optical and metallic clock distribution networks in new VLSI technologies
G Tosik, F Gaffiot, Z Lisik, I O'Connor, F Tissafi-Drissi
Electronics Letters 40 (3), 1, 2004
Thermal aware design method for vcsel-based on-chip optical interconnect
H Li, A Fourmigue, S Le Beux, X Letartre, I O'Connor, G Nicolescu
2015 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2015
Full-adder circuit design based on all-spin logic device
Q An, L Su, JO Klein, S Le Beux, I O'Connor, W Zhao
Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale …, 2015
Design, simulation, and characterization of a passive optical add-drop filter in silicon-on-insulator technology
A Kazmierczak, M Brière, E Drouard, P Bontoux, P Rojo-Romeo, ...
IEEE Photonics Technology Letters 17 (7), 1447-1449, 2005
Layout guidelines for 3D architectures including optical ring network-on-chip (ORNoC)
S Le Beux, J Trajkovic, I O'Connor, G Nicolescu
2011 IEEE/IFIP 19th International Conference on VLSI and System-on-Chip, 242-247, 2011
Towards reconfigurable optical networks on chip.
I O'Connor, M Briere, E Drouard, A Kazmierczak, F Tissafi-Drissi, ...
ReCoSoC 5, 121-128, 2005
An analog beam-forming circuit for ultrasound imaging using switched-current delay lines
B Stefanelli, I O'Connor, L Quiquerez, A Kaiser, D Billet
IEEE Journal of solid-state circuits 35 (2), 202-211, 2000
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