Systolic algorithms and a memory-based design approach for a unified architecture for the computation of DCT/DST/IDCT/IDST DF Chiper, MNS Swamy, MO Ahmad, T Stouraitis
IEEE Transactions on Circuits and Systems I: Regular Papers 52 (6), 1125-1137, 2005
94 2005 A systolic array architecture for the discrete sine transform DF Chiper, MNS Swamy, MO Ahmad, T Stouraitis
IEEE transactions on signal processing 50 (9), 2347-2354, 2002
65 2002 A novel VLSI DHT algorithm for a highly modular and parallel architecture DF Chiper
IEEE Transactions on Circuits and Systems II: Express Briefs 60 (5), 282-286, 2013
32 2013 Novel VLSI algorithm and architecture with good quantization properties for a high-throughput area efficient systolic array implementation of DCT DF Chiper, P Ungureanu
EURASIP Journal on Advances in Signal Processing 2011, 1-14, 2011
30 2011 An efficient unified framework for implementation of a prime-length DCT/IDCT with high throughput DF Chiper, MNS Swamy, MO Ahmad
IEEE transactions on signal processing 55 (6), 2925-2936, 2007
30 2007 An efficient systolic array algorithm for the VLSI implementation of a prime-length DHT DF Chiper, MNS Swamy, MO Ahmad
International Symposium on Signals, Circuits and Systems, 2005. ISSCS 2005 …, 2005
27 2005 Radix-2 fast algorithm for computing discrete Hartley transform of type III DF Chiper
IEEE Transactions on Circuits and Systems II: Express Briefs 59 (5), 297-301, 2012
25 2012 Novel systolic array design for discrete cosine transform with high throughput rate DF Chiper
1996 IEEE International Symposium on Circuits and Systems. Circuits and …, 1996
22 1996 A new systolic array algorithm for memory-based VLSI array implementation of DCT DF Chiper
Proceedings Second IEEE Symposium on Computer and Communications, 297-301, 1997
21 1997 Fast radix-2 algorithm for the discrete Hartley transform of type II DF Chiper
IEEE Signal Processing Letters 18 (11), 687-689, 2011
18 2011 A systolic array algorithm for an efficient unified memory-based implementation of the inverse discrete cosine and sine transforms DF Chiper
Proceedings 1999 International Conference on Image Processing (Cat …, 1999
18 1999 A New Systolic Array Algorithm and Architecture for the VLSI Implementation of IDST Based on a Pseudo-Band Correlation Structure. DF Chiper, A Cracan
Advances in Electrical & Computer Engineering 17 (1), 2017
16 2017 A new VLSI algorithm and architecture for the hardware implementation of type IV discrete cosine transform using a pseudo-band correlation structure D Chiper
Open Computer Science 1 (2), 243-250, 2011
14 2011 A new VLSI algorithm for a high-throughput implementation of type IV DCT DF Chiper
2016 International Conference on Communications (COMM), 17-20, 2016
13 2016 A parallel VLSI algorithm for a high throughput systolic array VLSI implementation of type IV DCT DF Chiper
2009 International Symposium on Signals, Circuits and Systems, 1-4, 2009
11 2009 A new approach for a unified architecture for type IV DCT/DST with an efficient incorporation of obfuscation technique DF Chiper, LT Cotorobai
Electronics 10 (14), 1656, 2021
9 2021 A low complexity algorithm for the VLSI implementation of DST based on band-correlation structures DF Chiper, LT Cotorobai
2019 International Symposium on Signals, Circuits and Systems (ISSCS), 1-4, 2019
7 2019 A unified VLSI algorithm for a high performance systolic array implementation of type IV DCT/DST DF Chiper, MO Ahmad, MNS Swamy
International Symposium on Signals, Circuits and Systems ISSCS2013, 1-4, 2013
7 2013 A new VLSI algorithm for type IV DCT for an efficient implementation of obfuscation technique LT Cotorobai, DF Chiper
2020 43rd International Conference on Telecommunications and Signal …, 2020
6 2020 A Structured Dual Split-Radix Algorithm for the Discrete Hartley Transform of Length DF Chiper
Circuits, Systems, and Signal Processing 37, 290-304, 2018
6 2018 