| High-throughput multi-core LDPC decoders based on x86 processor B Le Gal, C Jego IEEE Transactions on Parallel and Distributed Systems 27 (5), 1373-1386, 2016 | 73 | 2016 |
| Automatic low-cost IP watermarking technique based on output mark insertions B Le Gal, L Bossuet Design Automation for Embedded Systems 16, 71-92, 2012 | 72 | 2012 |
| Aff3ct: A fast forward error correction toolbox! A Cassagne, O Hartmann, M Leonardon, K He, C Leroux, R Tajan, ... SoftwareX 10, 100345, 2019 | 67 | 2019 |
| Multi-gb/s software decoding of polar codes B Le Gal, C Leroux, C Jego IEEE Transactions on Signal Processing 63 (2), 349-359, 2015 | 61 | 2015 |
| A high throughput efficient approach for decoding LDPC codes onto GPU devices B Le Gal, C Jego, J Crenne IEEE Embedded Systems Letters 6 (2), 29-32, 2014 | 48 | 2014 |
| Dynamic memory access management for high-performance DSP applications using high-level synthesis B Le Gal, E Casseau, S Huet IEEE Transactions on Very Large Scale Integration (VLSI) Systems 16 (11 …, 2008 | 44 | 2008 |
| Fast converging ADMM-penalized algorithm for LDPC decoding I Debbabi, B Le Gal, N Khouja, F Tlili, C Jego IEEE Communications Letters 20 (4), 648-651, 2016 | 37 | 2016 |
| QBox: an industrial solution for virtual platform simulation using QEMU and SystemC TLM-2.0 G Delbergue, M Burton, F Konrad, B Le Gal, C Jego 8th European Congress on Embedded Real Time Software and Systems (ERTS 2016), 2016 | 37 | 2016 |
| C-based rapid prototyping for digital signal processing E Casseau, B Le Gal, P Bomel, C Jego, S Huet, E Martin Proceedings of the European Signal Processing Conference, 1-4, 2005 | 35 | 2005 |
| Lowering the error floor of turbo codes with CRC verification T Tonnellier, C Leroux, B Le Gal, B Gadat, C Jego, N Van Wambeke IEEE Wireless Communications Letters 5 (4), 404-407, 2016 | 31 | 2016 |
| High-level synthesis for the design of FPGA-based signal processing systems E Casseau, B Le Gal 2009 International Symposium on Systems, Architectures, Modeling, and …, 2009 | 28 | 2009 |
| High-throughput LDPC decoder on low-power embedded processors B Le Gal, C Jego IEEE Communications Letters 19 (11), 1861-1864, 2015 | 25 | 2015 |
| Design of multi-mode application-specific cores based on high-level synthesis E Casseau, B Le Gal Integration 45 (1), 9-21, 2012 | 24 | 2012 |
| FPGA based system for automatic cDNA microarray image processing B Belean, M Borda, B Le Gal, R Terebes Computerized Medical Imaging and Graphics 36 (5), 419-429, 2012 | 23 | 2012 |
| Word-length aware DSP hardware design flow based on high-level synthesis B Le Gal, E Casseau Journal of signal processing systems 62, 341-357, 2011 | 23 | 2011 |
| Beyond Gbps Turbo decoder on multi-core CPUs A Cassagne, T Tonnellier, C Leroux, B Le Gal, O Aumage, D Barthou Turbo Codes and Iterative Information Processing (ISTC), 2016 9th …, 2016 | 21 | 2016 |
| An efficient, portable and generic library for successive cancellation decoding of polar codes A Cassagne, B Le Gal, C Leroux, O Aumage, D Barthou Languages and Compilers for Parallel Computing: 28th International Workshop …, 2016 | 20 | 2016 |
| Assertion support in high-level synthesis design flow A Ribon, B Le Gal, C Jégo, D Dallet FDL 2011 Proceedings, 1-8, 2011 | 19 | 2011 |
| A Reconfigurable Multi-core Cryptoprocessor for Multi-channel Communication Systems M Grand, L Bossuet, G Gogniat, B Le Gal, JP Delahaye, D Dallet Parallel and Distributed Processing Workshops and Phd Forum (IPDPSW), 2011 …, 2011 | 19 | 2011 |
| Bit-width aware high-level synthesis for digital signal processing systems B Le Gal, C Andriamisaina, E Casseau 2006 IEEE International SOC Conference, 175-178, 2006 | 19 | 2006 |
Christophe JEGOProfessor IMS LaboratoryVerified email at enseirb-matmeca.fr
