Nasim Farahini
Nasim Farahini
Qamcom Research and Technology
Adresă de e-mail confirmată pe kth.se
Citat de
Citat de
Energy-aware coarse-grained reconfigurable architectures using dynamically reconfigurable isolation cells
SMAH Jafri, O Bag, A Hemani, N Farahini, K Paul, J Plosila, H Tenhunen
International Symposium on Quality Electronic Design (ISQED), 104-111, 2013
39.9 GOPs/watt multi-mode CGRA accelerator for a multi-standard basestation
N Farahini, S Li, MA Tajammul, MA Shami, G Chen, A Hemani, W Ye
2013 IEEE International Symposium on Circuits and Systems (ISCAS), 1448-1451, 2013
System level synthesis of hardware for DSP applications using pre-characterized function implementations
S Li, N Farahini, A Hemani, K Rosvall, I Sander
2013 International Conference on Hardware/Software Codesign and System …, 2013
A Scalable Custom Simulation Machine for the Bayesian Confidence Propagation Neural Network Model of the Brain
N Farahini, A Hemani, A Lansner, F Clermidy, C Svensson
Design Automation Conference (ASP-DAC), 2014 19th Asia and South Pacific …, 2014
Parallel distributed scalable runtime address generation scheme for a coarse grain reconfigurable computation and storage fabric
N Farahini, A Hemani, H Sohofi, SMAH Jafri, MA Tajammul, K Paul
Microprocessors and Microsystems 38 (8), 788-802, 2014
Silago-cog: Coarse-grained grid-based design for near tape-out power estimation accuracy at high level
SMAH Jafri, N Farahini, A Hemani
2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 25-31, 2017
The silago solution: Architecture and design methods for a heterogeneous dark silicon aware coarse grain reconfigurable fabric
A Hemani, N Farahini, SMAH Jafri, H Sohofi, S Li, K Paul
The Dark Side of Silicon: Energy Efficient Computing in the Dark Silicon Era …, 2017
Spiking Brain Models: Computation, Memory and Communication Constraints for Custom Hardware Implementation
A Lansner, A Hemani, N Farahini
Design Automation Conference (ASP-DAC), 2014 19th Asia and South Pacific …, 2014
Physical Design Aware System Level Synthesis of Hardware
N Farahini, A Hemani, H Sohofi, S Li
Architecture and implementation of dynamic parallelism, voltage and frequency scaling (PVFS) on CGRAs
SMAH Jafri, O Ozbag, N Farahini, K Paul, A Hemani, J Plosila, ...
ACM Journal on Emerging Technologies in Computing Systems (JETC) 11 (4), 1-29, 2015
Global control and storage synthesis for a system level synthesis approach
S Li, N Farahini, A Hemani
2013 IEEE 21st Annual International Symposium on Field-Programmable Custom …, 2013
Distributed Runtime Computation of Constraints for Multiple Inner Loops
N Farahini, A Hemani, K Paul
Digital System Design (DSD), 2013 Euromicro, 2013, 2013
A conceptual custom super-computer design for real-time simulation of human brain
N Farahini, A Hemani
2013 21st Iranian conference on electrical engineering (ICEE), 1-6, 2013
Algosil: A high level synthesis tool targeting micro-architecture level physical design platform
N Farahini, A Hemani, H Sohofi
KTH Royal Institute of Technology, 2016
Atomic stream computation unit based on micro-thread level parallelism
N Farahini, A Hemani
2015 IEEE 26th International Conference on Application-specific Systems …, 2015
SiLago: Enabling System Level Automation Methodology to Design Custom High-Performance Computing Platforms: Toward Next Generation Hardware Synthesis Methodologies
N Farahini
KTH Royal Institute of Technology, 2016
Customization methodology of a Coarse Grained Reconfigurable architecture
SP Azad, N Farahini, A Hemani
2014 NORCHIP, 1-4, 2014
An improved hierarchical design flow for coarse grain regular fabrics
N Farahini
SiLago: A Structured Layout Scheme to Enable Efficient High Level and System Level Synthesis
N Farahini, A Hemani, S Jafri, H Sohofi
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