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Vaughn Betz
Vaughn Betz
Adresă de e-mail confirmată pe eecg.utoronto.ca
Titlu
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Architecture and CAD for deep-submicron FPGAs
V Betz, J Rose, A Marquardt
Springer Science & Business Media, 2012
18082012
VPR: A new packing, placement and routing tool for FPGA research
V Betz, J Rose
International Workshop on Field Programmable Logic and Applications, 213-222, 1997
15691997
VTR 7.0: Next generation architecture and CAD system for FPGAs
J Luu, J Goeders, M Wainberg, A Somerville, T Yu, K Nasartschuk, M Nasr, ...
ACM Transactions on Reconfigurable Technology and Systems (TRETS) 7 (2), 1-30, 2014
4622014
Using cluster-based logic blocks and timing-driven packing to improve FPGA speed and density
A Marquardt, V Betz, J Rose
Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field …, 1999
3651999
Timing-driven placement for FPGAs
A Marquardt, V Betz, J Rose
Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field …, 2000
3632000
The Stratix II logic and routing architecture
D Lewis, E Ahmed, G Baeckler, V Betz, M Bourgeault, D Cashman, ...
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field …, 2005
2642005
FPGA routing architecture: Segmentation and buffering to optimize speed and density
V Betz, J Rose
Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field …, 1999
2511999
Vtr 8: High-performance cad and customizable fpga architecture modelling
KE Murray, O Petelin, S Zhong, JM Wang, M Eldafrawy, JP Legault, E Sha, ...
ACM Transactions on Reconfigurable Technology and Systems (TRETS) 13 (2), 1-55, 2020
2162020
Cluster-based logic blocks for FPGAs: Area-efficiency vs. input sharing and size
V Betz, J Rose
Proceedings of CICC 97-Custom Integrated Circuits Conference, 551-554, 1997
2121997
The stratix routing and logic architecture
D Lewis, V Betz, D Jefferson, A Lee, C Lane, P Leventis, S Marquardt, ...
Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field …, 2003
1712003
A fast routability-driven router for FPGAs
JS Swartz, V Betz, J Rose
Proceedings of the 1998 ACM/SIGDA sixth international symposium on Field …, 1998
1681998
How much logic should go in an FPGA logic block
V Betz, J Rose
IEEE Design & Test of Computers 15 (1), 10-15, 1998
1661998
Comparing fpga vs. custom cmos and the impact on processor microarchitecture
H Wong, V Betz, J Rose
Proceedings of the 19th ACM/SIGDA international symposium on Field …, 2011
1562011
EDA for IC implementation, circuit design, and process technology
L Lavagno, L Scheffer, G Martin
CRC, 2006
149*2006
The Stratix-II Routing and Logic Architecture
D Lewis, V Betz, D Jefferson, A Lee, C Lane, P Leventis, S Marquardt, ...
Proceedings of the 2005 ACM/SIGDA 13th International Symposium on Field …, 2005
1422005
Titan: Enabling large and complex benchmarks in academic CAD
KE Murray, S Whitty, S Liu, J Luu, V Betz
2013 23rd International Conference on Field programmable Logic and …, 2013
1362013
Directional bias and non-uniformity in FPGA global routing architectures
V Betz, J Rose
Proceedings of International Conference on Computer Aided Design, 652-659, 1996
1341996
Speed and area tradeoffs in cluster-based FPGA architectures
A Marquardt, V Betz, J Rose
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 8 (1), 84-93, 2000
1322000
APPARATUS AND METHODS FOR ADJUSTING PERFORMANCE OF INTEGRATED CIRCUITS
D LEWIS, V BETZ, I RAHIM, P MCELHENY
WO Patent WO/2005/116,878, 2005
120*2005
Error correction for programmable logic integrated circuits
D Lewis, V Betz
US Patent 7,328,377, 2008
118*2008
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