Pillement Sébastien

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Olivier SentieysProfessor, University of Rennes, IRISA, INRIA, FranceAdresă de e-mail confirmată pe irisa.fr
Raphael DavidCEA, ENSSATAdresă de e-mail confirmată pe cea.fr
Didier DemignyUniv RennesAdresă de e-mail confirmată pe univ-rennes1.fr
Stanislaw J. PiestrakProfessor of Computer Engineering, Université de Lorraine, FranceAdresă de e-mail confirmată pe univ-lorraine.fr
Philippe MILLETHead of the Innovation Hub of the Numerical Unit of Excellence at NexterAdresă de e-mail confirmată pe philippemillet.net
Prévotet Jean-ChristopheIETR Insa de RennesAdresă de e-mail confirmată pe insa-rennes.fr
Kim GrüttnerGerman Aerospace Center (DLR)Adresă de e-mail confirmată pe dlr.de
Ralf StemmerGerman Aerospace Center (DLR)Adresă de e-mail confirmată pe dlr.de
François VerdierUniversité de Nice Sophia-Antipolis, CNRS LEAT UMR 7248Adresă de e-mail confirmată pe unice.fr
Sebastien FaucouUniversité de NantesAdresă de e-mail confirmată pe univ-nantes.fr
Syed Mohammad Asad Hassan JafriEricssonAdresă de e-mail confirmată pe kth.se
Pascal ChargéPolytech Nantes - Université de NantesAdresă de e-mail confirmată pe univ-nantes.fr
Bertrand GranadoSobonne universitéAdresă de e-mail confirmată pe upmc.fr
Daniel HolcombAssociate Professor, University of MassachusettsAdresă de e-mail confirmată pe engin.umass.edu
Russell TessierUniversity of MassachusettsAdresă de e-mail confirmată pe umass.edu
Maciej CiesielskiProfessor of ELectrical and Computer EngineeringAdresă de e-mail confirmată pe ecs.umass.edu
Maria Méndez RealPolytech Université de Nantes - IETR UMR CNRS 6164Adresă de e-mail confirmată pe univ-nantes.fr
Atif YasinUniversity of Massachusetts AmherstAdresă de e-mail confirmată pe umass.edu
Benoît MiramondFull professor, Université Côte d'Azur, LEATAdresă de e-mail confirmată pe univ-cotedazur.fr
Istas PratomoLecturer of Electronics and Telecommunications Network, Sepuluh Nopember Institut of TechnologyAdresă de e-mail confirmată pe ee.its.ac.id

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Pillement Sébastien

Professeur des Universités, Université de Nantes

Adresă de e-mail confirmată pe univ-nantes.fr - Pagina de pornire

reconfigurable computing network-on-chip dynamic management Reliability


Titlu Sortați după descrierea bibliografică Sortați după an Sortați după titlu	Citat de Citat de	Anul
FPGA side channel attacks without physical access C Ramesh, SB Patil, SN Dhanuskodi, G Provelengios, S Pillement, ... 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom …, 2018	115	2018
DART: a dynamically reconfigurable architecture dealing with future mobile telecommunications constraints R David, D Chillet, S Pillement, O Sentieys IEEE International Parallel and Distributed Processing Symposium, 2003	75	2003
Low Overhead Fault-Tolerance Technique for Dynamically Reconfigurable Softcore Processor H Pham, S Pillement, S Piestrak IEEE Transactions on Computers 99, 1-1, 2012	69	2012
DART: a Functional-Level Reconfigurable Architecture for High Energy Efficiency S Pillement, O Sentieys, R David EURASIP Journal on Embedded Systems, 5, 2008	44	2008
Design of a Fault-Tolerant Coarse-Grained Reconfigurable Architecture: A Case Study S Jafri, SJ Piestrak, O Sentieys, S Pillement Quality Electronic Design (ISQED), 2010 11th International Symposium on, 845-852, 2010	40*	2010
Towards Future Adaptive Multiprocessor Systems-On-Chip: an Innovative Approach for Flexible Architectures F Lemonnier, P Millet, GM Almeida, M Hübner, J Becker, S Pillement, ... Embedded Computer Systems: Architectures, MOdeling and Simulation (SAMOS), 2012	38	2012
UPaRC—Ultra-Fast Power-aware Reconfiguration Controller R Bonamy, HM Pham, S Pillement, D Chillet Design and Test in Europe, 2012	35	2012
Dart: A dynamically reconfigurable architecture dealing with next generation telecommunications constraints R David, D Chillet, S Pillement, O Sentieys 9th IEEE Reconfigurable Architecture Workshop RAW, 2002	29	2002
Error recovery technique for coarse-grained reconfigurable architectures MM Azeem, SJ Piestrak, O Sentieys, S Pillement 14th IEEE International Symposium on Design and Diagnostics of Electronic …, 2011	26	2011
Area efficient temporal coding schemes for reducing crosstalk effects JM Philippe, S Pillement, O Sentieys 7th International Symposium on Quality Electronic Design (ISQED'06), 6 pp.-339, 2006	26	2006
A low-power and high-speed quaternary interconnection link using efficient converters JM Philippe, S Pillement, O Sentieys 2005 IEEE International Symposium on Circuits and Systems, 4689-4692, 2005	26	2005
Flexible interconnection network for dynamically and partially reconfigurable architectures L Devaux, S Ben Sassi, S Pillement, D Chillet, D Demigny International Journal of Reconfigurable Computing 2010, 2010	25	2010
Designing efficient codecs for bus-invert berger code for fully asymmetric communication SJ Piestrak, S Pillement, O Sentieys iEEE transactions on circuits and systems ii: Express Briefs 57 (10), 777-781, 2010	20	2010
OveRSoC: a framework for the exploration of RTOS for RSoC platforms B Miramond, E Huck, F Verdier, A Benkhelifa, B Granado, T Lefebvre, ... International Journal of Reconfigurable Computing 2009, 1-26, 2009	20	2009
Method and device for programming a FPGA O Sentieys, S Pillement, C Huriaux, A Courtay US Patent 9,754,061, 2017	18	2017
Gradient—An adaptive fault-tolerant routing algorithm for 2D mesh network-on-chips I Pratomo, S Pillement Proceedings of the 2012 Conference on Design and Architectures for Signal …, 2012	18	2012
Real-Time Scheduling on Heterogeneous System-on-Chip Architectures Using an Optimized Artificial Neural Network D Chillet, A Eiche, S Pillement, O Sentieys Journal of Systems Architecture 57 (4), 340--353, 2011	18	2011
A compilation framework for a dynamically reconfigurable architecture R David, D Chillet, S Pillement, O Sentieys Field-Programmable Logic and Applications: Reconfigurable Computing Is Going …, 2002	18	2002
A fault-tolerant layer for dynamically reconfigurable multi-processor system-on-chip HM Pham, S Pillement, D Demigny 2009 International Conference on Reconfigurable Computing and FPGAs, 284-289, 2009	17	2009
Task placement for dynamic and partial reconfigurable architecture A Eiche, D Chillet, S Pillement, O Sentieys 2010 Conference on Design and Architectures for Signal and Image Processing …, 2010	16	2010

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