Atif Yasin
Atif Yasin
Adresă de e-mail confirmată pe umass.edu
Citat de
Citat de
Understanding algebraic rewriting for arithmetic circuit verification: a bit-flow model
M Ciesielski, T Su, A Yasin, C Yu
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2019
Formal verification of truncated multipliers using algebraic approach and re-synthesis
T Su, C Yu, A Yasin, M Ciesielski
2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 415-420, 2017
Functional verification of hardware dividers using algebraic model
A Yasin, T Su, S Pillement, M Ciesielski
2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration …, 2019
Formal verification of integer dividers: Division by a constant
A Yasin, T Su, S Pillement, M Ciesielski
2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 76-81, 2019
Improving software requirements reasoning by novices: a story‐based approach
R Fatima, A Yasin, L Liu, J Wang, W Afzal, A Yasin
IET Software 13 (6), 564-574, 2019
Computer algebraic approach to verification and debugging of Galois field multipliers
T Su, A Yasin, C Yu, M Ciesielski
2018 IEEE International Symposium on Circuits and Systems (ISCAS), 1-5, 2018
Synergistic timing speculation for multi-threaded programs
A Yasin, JJ Zhang, H Chen, S Garg, S Roy, K Chakraborty
Proceedings of the 53rd Annual Design Automation Conference, 1-6, 2016
SPEAR: hardware-based implicit rewriting for square-root circuit verification
A Yasin, T Su, S Pillement, M Ciesielski
2020 Design, Automation & Test in Europe Conference & Exhibition (DATE), 532-537, 2020
Formal verification of divider and square-root arithmetic circuits using computer algebra methods
A Yasin
Spectral approach to verifying non-linear arithmetic circuits
C Yu, T Su, A Yasin, M Ciesielski
Proceedings of the 24th Asia and South Pacific Design Automation Conference …, 2019
Rewriting Environment for Arithmetic Circuit Verification.
C Yu, A Yasin, T Su, A Mishchenko, MJ Ciesielski
LPAR, 656-666, 2018
How to Overcome Communication Barriers in Global Software Development?
A Yasin, A Yasin
Ubiquitous Computing and Communication Journal 8 (1), 1359-1365, 2013
Formal verification of divider circuits by hardware reduction
A Yasin, T Su, S Pillement, M Ciesielski
2023 19th International Conference on Synthesis, Modeling, Analysis and …, 2023
Formal verification of constrained arithmetic circuits using computer algebraic approach
T Su, A Yasin, S Pillement, M Ciesielski
2020 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 386-391, 2020
How Shared Leadership Can be Introduced in a Software Project Team? An Exploratory Study
A Yasin, A Yasin
International Journal of Scientific & Engineering Research 4 (5), 2013
Functional Verification of Arithmetic Circuits: Survey of Formal Methods
M Ciesielski, A Yasin, J Dasari
2022 25th International Symposium on Design and Diagnostics of Electronic …, 2022
Dual Approach to Solving SAT in Hardware
DD Narasimharaju, RSS Rao, AS Waingade, A Yasin, M Ciesielski
2020 15th Design & Technology of Integrated Systems in Nanoscale Era (DTIS), 1-6, 2020
ScholarWorks@ UMass Amherst
S Carson
Aatreyi Bal Abhranil Maiti Andrea Calimera Ao Ren
A Roohi, A Yasin, A Bose, A Aysu, AF Tabrizi, B Behazin, B Liang, B Li, ...
Does Familiarity within the Distributed Team Improve Performance? Exploratory Study.
A Yasin, A Yasin
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