Dilip Vasudevan
Dilip Vasudevan
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Reversible-logic design with online testability
DP Vasudevan, PK Lala, J Di, JP Parkerson
IEEE transactions on instrumentation and measurement 55 (2), 406-414, 2006
Self-checking carry-select adder design based on two-rail encoding
DP Vasudevan, PK Lala, JP Parkerson
IEEE Transactions on Circuits and Systems I: Regular Papers 54 (12), 2696-2705, 2007
A 6.45 Self-Powered SoC With Integrated Energy-Harvesting Power Management and ULP Asymmetric Radios for Portable Biomedical Systems
A Roy, A Klinefelter, FB Yahya, X Chen, LP Gonzalez-Guerrero, CJ Lukas, ...
IEEE Transactions on biomedical circuits and systems 9 (6), 862-874, 2015
Online testable reversible logic circuit design using NAND blocks
DP Vasudevan, PK Lala, JP Parkerson
19th IEEE International Symposium on Defect and Fault Tolerance in VLSI …, 2004
A computational temporal logic for superconducting accelerators
G Tzimpragos, D Vasudevan, N Tsiskaridze, G Michelogiannakis, ...
Proceedings of the Twenty-Fifth International Conference on Architectural …, 2020
A novel approach for on-line testable reversible logic circuit design
DP Vasudevan, PK Lala, JP Parkerson
13th Asian Test Symposium, 325-330, 2004
A technique for modular design of self-checking carry-select adder
DP Vasudevan, PK Lala
20th IEEE International Symposium on Defect and Fault Tolerance in VLSI …, 2005
Boosted race trees for low energy classification
G Tzimpragos, A Madhavan, D Vasudevan, D Strukov, T Sherwood
Proceedings of the Twenty-Fourth International Conference on Architectural …, 2019
Global built-in self-repair for 3D memories with redundancy sharing and parallel testing
X Wang, D Vasudevan, HHS Lee
2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE …, 2012
Temporal computing with superconductors
G Tzimpragos, J Volk, D Vasudevan, N Tsiskaridze, G Michelogiannakis, ...
IEEE Micro 41 (3), 71-79, 2021
CMOS realization of online testable reversible logic gates
DP Vasudevan, PK Lala, JP Parkerson
IEEE Computer Society Annual Symposium on VLSI: New Frontiers in VLSI Design …, 2005
10x10: A case study in highly-programmable and energy-efficient heterogeneous federated architecture
AA Chien, T Thanh-Hoang, D Vasudevan, Y Fang, A Shambayati
ACM SIGARCH Computer Architecture News 43 (3), 2-9, 2015
Design and analysis of a novel 8T SRAM cell for adiabatic and non-adiabatic operations
J Chen, D Vasudevan, E Popovici, M Schellekens, P Gillen
2010 17th IEEE International Conference on Electronics, Circuits and Systems …, 2010
Generalized pattern matching micro-engine
Y Fang, R ur Rasool, D Vasudevan, AA Chien
4th Workshop on Architectures and Systems for Big Data (ASBD) held with ISCA 14, 2014
Design of a Low Power, Sub-Threshold, Asynchronous Arithmetic Logic Unit Using a Bidirectional Adder
J Chen, D Vasudevan, E Popovici, M Schellekens
2011 14th Euromicro Conference on Digital System Design, 301-308, 2011
SRNoC: A statically-scheduled circuit-switched superconducting race logic NoC
G Michelogiannakis, D Lyles, P Gonzalez-Guerrero, M Bautista, ...
2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS …, 2021
Ultra low power Booth multiplier using asynchronous logic
J Chen, E Popovici, D Vasudevan, M Schellekens
2012 IEEE 18th International Symposium on Asynchronous Circuits and Systems …, 2012
Reversible online BIST using bidirectional BILBO
J Chen, DP Vasudevan, E Popovici, M Schellekens
Proceedings of the 7th ACM international conference on Computing frontiers …, 2010
A Reversible MIPS multi-cycle control FSM design
D Vasudevan, M Goudarzi, E Popovici, M Schellekens
2009 1st Asia Symposium on Quality Electronic Design, 336-342, 2009
Towards an integrated strategy to preserve digital computing performance scaling using emerging technologies
D Vasudevan, A Butko, G Michelogiannakis, D Donofrio, J Shalf
High Performance Computing: ISC High Performance 2017 International …, 2017
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