| A reference-less single-loop half-rate binary CDR MS Jalali, A Sheikholeslami, M Kibune, H Tamura IEEE Journal of Solid-State Circuits 50 (9), 2037-2047, 2015 | 50 | 2015 |
| A high-efficiency CMOS rectifier for low-power RFID tags AS Bakhtiar, MS Jalali, S Mirabbasi 2010 IEEE International Conference on RFID (IEEE RFID 2010), 83-88, 2010 | 47 | 2010 |
| An 8–11 Gb/s reference-less bang-bang CDR enabled by “Phase reset” R Shivnaraine, MS Jalali, A Sheikholeslami, M Kibune, H Tamura IEEE Transactions on Circuits and Systems I: Regular Papers 61 (7), 2129-2138, 2014 | 27 | 2014 |
| On-chip measurement of clock and data jitter with sub-picosecond accuracy for 10 Gb/s multilane CDRs J Liang, MS Jalali, A Sheikholeslami, M Kibune, H Tamura IEEE Journal of Solid-State Circuits 50 (4), 845-855, 2014 | 26 | 2014 |
| An 8mW frequency detector for 10Gb/s half-rate CDR using clock phase selection MS Jalali, R Shivnaraine, A Sheikholeslami, M Kibune, H Tamura Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 1-8, 2013 | 22 | 2013 |
| A 4-Lane 1.25-to-28.05 Gb/s multi-standard 6pJ/b 40dB transceiver in 14nm FinFET with independent TX/RX rate support MS Jalali, MH Taghavi, A Melaren, J Pham, K Farzan, D Diclemente, ... 2018 IEEE International Solid-State Circuits Conference-(ISSCC), 106-108, 2018 | 16 | 2018 |
| An RF power harvesting system with input-tuning for long-range RFID tags AS Bakhtiar, MS Jalali, S Mirabbasi Proceedings of 2010 IEEE International Symposium on Circuits and Systems …, 2010 | 11 | 2010 |
| A charge-pump with a high output swing for PLL and CDR applications MS Jalali, AS Bakhtiar, S Mirabbasi Proceedings of the 8th IEEE International NEWCAS Conference 2010, 297-300, 2010 | 10 | 2010 |
| A 3x blind ADC-based CDR MS Jalali, C Ting, B Abiri, A Sheikholeslami, M Kibune, H Tamura 2013 IEEE Asian Solid-State Circuits Conference (A-SSCC), 349-352, 2013 | 5 | 2013 |
| High speed ADCs for wireline applications MS Jalali, M Hossain, K Dyer, S Sadr 2017 IEEE 60th International Midwest Symposium on Circuits and Systems …, 2017 | 4 | 2017 |
| A 3x blind ADC-based CDR for a 20 dB loss channel MS Jalali, C Ting, J Liang, A Sheikholeslami, M Kibune, H Tamura IEEE Transactions on Circuits and Systems I: Regular Papers 62 (6), 1658-1667, 2015 | 4 | 2015 |
| On-chip measurement of data jitter with sub-picosecond accuracy for 10Gb/s multilane CDRs J Liang, MS Jalali, A Sheikholeslami, M Kibune, H Tamura 2014 Symposium on VLSI Circuits Digest of Technical Papers, 1-2, 2014 | 3 | 2014 |
| A hybrid phase-locked loop for clock and data recovery applications MS Jalali University of British Columbia, 2010 | 3 | 2010 |
| 4×, 3‐level, blind ADC‐based receiver N Kovacevic, MS Jalali, J Liang, C Ting, A Sheikholeslami, M Kibune, ... Electronics Letters 51 (7), 551-553, 2015 | 2 | 2015 |
| A blind ADC-based CDR with digital data interpolation and adaptive CTLE and DFE C Ting, MS Jalali, A Sheikholeslami, M Kibune, H Tamura Proceedings of the IEEE 2014 Custom Integrated Circuits Conference, 1-4, 2014 | 1 | 2014 |
| A hybrid phase-locked loop for CDR Applications MS Jalali, AS Bakhtiar, S Mirabbasi 2011 IEEE International Symposium of Circuits and Systems (ISCAS), 2533-2536, 2011 | 1 | 2011 |
| Live offset cancellation of the decision feedback equalization data slicers MS Jalali, M Van Ierssel US Patent 12,057,975, 2024 | | 2024 |
| System and method for recovering a clock signal E Chong, MS Jalali, B Dehlaghi US Patent 11,675,386, 2023 | | 2023 |
| Live offset cancellation of the decision feedback equalization data slicers MS Jalali, M Van Ierssel US Patent 11,671,286, 2023 | | 2023 |
| 4×, 3-level, blind ADC-based receiver H Tamura, A Sheikholeslami, M Kibune, J Liang, C Ting, N Kovacevic, ... Electronics Letters 51 (7), 551-553, 2015 | | 2015 |
