| A 6-bit 1.2-GS/s low-power flash-ADC in 0.13-/spl mu/m digital CMOS C Sandner, M Clara, A Santner, T Hartig, F Kuttner IEEE Journal of Solid-State Circuits 40 (7), 1499-1505, 2005 | 282 | 2005 |
| Transformer-based dual-mode voltage-controlled oscillators A Bevilacqua, FP Pavan, C Sandner, A Gerosa, A Neviani IEEE Transactions on Circuits and Systems II: Express Briefs 54 (4), 293-297, 2007 | 174 | 2007 |
| On the jitter requirements of the sampling clock for analog-to-digital converters N Da Dalt, M Harteneck, C Sandner, A Wiesbauer IEEE Transactions on Circuits and Systems I: Fundamental Theory and …, 2002 | 174 | 2002 |
| A wimedia/mboa-compliant cmos rf transceiver for uwb C Sandner, S Derksen, D Draxelmayr, S Ek, V Filimon, G Leach, S Marsili, ... IEEE Journal of Solid-State Circuits 41 (12), 2787-2794, 2006 | 129 | 2006 |
| A fully integrated differential CMOS LNA for 3-5-GHz ultrawideband wireless receivers A Bevilacqua, C Sandner, A Gerosa, A Neviani IEEE Microwave and wireless components letters 16 (3), 134-136, 2006 | 129 | 2006 |
| Analysis and design of an integrated notch filter for the rejection of interference in UWB systems A Vallese, A Bevilacqua, C Sandner, M Tiebout, A Gerosa, A Neviani IEEE Journal of Solid-State Circuits 44 (2), 331-343, 2009 | 115 | 2009 |
| Fully integrated distributed power amplifier in CMOS technology, optimized for UWB transmitters C Grewing, K Winterberg, S van Waasen, M Friedrich, GL Puma, ... 2004 IEE Radio Frequency Integrated Circuits (RFIC) Systems. Digest of …, 2004 | 81 | 2004 |
| A subpicosecond jitter PLL for clock generation in 0.12-μm digital CMOS N Da Dalt, C Sandner IEEE Journal of Solid-State Circuits 38 (7), 1275-1278, 2003 | 78* | 2003 |
| A 3.4-7 GHz transformer-based dual-mode wideband VCO A Bevilacqua, FP Pavan, C Sandner, A Gerosa, A Neviani 2006 Proceedings of the 32nd European Solid-State Circuits Conference, 440-443, 2006 | 68 | 2006 |
| UWB fast-hopping frequency generation based on sub-harmonic injection locking S Dal Toso, A Bevilacqua, M Tiebout, S Marsili, C Sandner, A Gerosa, ... IEEE Journal of Solid-State Circuits 43 (12), 2844-2852, 2008 | 59 | 2008 |
| A 0.13/spl mu/m CMOS LNA with Integrated Balun and Notch Filter for 3-to-5GHz UWB Receivers A Bevilacqua, A Vallese, C Sandner, M Tiebout, A Gerosa, A Neviani 2007 IEEE International Solid-State Circuits Conference. Digest of Technical …, 2007 | 51 | 2007 |
| A fully integrated 13 GHz/spl Delta//spl Sigma/fractional-n PLL in 0.13/spl mu/m CMOS M Tiebout, C Sandner, HD Wohlmuth, N Da Dalt, E Thaller 2004 IEEE International Solid-State Circuits Conference (IEEE Cat. No …, 2004 | 42 | 2004 |
| Oscillator and method for generating an oscillator signal A Bevilacqua, FP Pavan, C Sandner US Patent 7,423,495, 2008 | 38 | 2008 |
| Digital phase-locked loop N Da Dalt, C Sandner US Patent 6,970,046, 2005 | 32 | 2005 |
| Circuit for the glitch-free changeover of digital signals C Sandner US Patent 6,075,392, 2000 | 32 | 2000 |
| Overvoltage protection for a synchronous power rectifier C Sandner, M Agostinelli US Patent 9,755,423, 2017 | 30 | 2017 |
| 5.8 A digitally assisted single-point-calibration CMOS bandgap voltage reference with a 3σ inaccuracy of±0.08% for fuel-gauge applications G Maderbacher, S Marsili, M Motz, T Jackum, J Thielmann, H Hassander, ... 2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of …, 2015 | 30 | 2015 |
| Automatic dead time optimization in a high frequency DC-DC buck converter in 65 nm CMOS G Maderbacher, T Jackum, W Pribyl, M Wassermann, A Petschar, ... 2011 Proceedings of the ESSCIRC (ESSCIRC), 487-490, 2011 | 30 | 2011 |
| Dead-time optimization of DC-DC converters C Sandner, G Maderbacher US Patent 9,712,046, 2017 | 29 | 2017 |
| System and method for generating signals with a preselected frequency relationship in two steps C Sandner, S Ek, S Marsili US Patent 7,602,254, 2009 | 28 | 2009 |
Andrea BevilacquaUniversity of PadovaAdresă de e-mail confirmată pe dei.unipd.it
