Laura Pozzi
Laura Pozzi
Full Professor of Computer Science, USI Lugano, Switzerland
Adresă de e-mail confirmată pe usi.ch - Pagina de pornire
Citat de
Citat de
Automatic application-specific instruction-set extensions under microarchitectural constraints
K Atasu, L Pozzi, P Ienne
Proceedings of the 40th annual Design Automation Conference, 256-261, 2003
Exact and approximate algorithms for the extension of embedded processor instruction sets
L Pozzi, K Atasu, P Ienne
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2006
EGRA: A coarse grained reconfigurable architectural template
G Ansaloni, P Bonzini, L Pozzi
IEEE Transactions on Very Large Scale Integration (VLSI) Systems 19 (6 …, 2010
Seamless hardware-software integration in reconfigurable computing systems
M Vuletid, L Pozzi, P Ienne
IEEE Design & Test of Computers 22 (2), 102-113, 2005
Exploiting pipelining to relax register-file port constraints of instruction-set extensions
L Pozzi, P Ienne
Proceedings of the 2005 international conference on Compilers, architectures …, 2005
Automatic instruction set extension and utilization for embedded processors
A Peymandoust, L Pozzi, P Ienne, G De Micheli
Proceedings IEEE International Conference on Application-Specific Systems …, 2003
A DAG-based design approach for reconfigurable VLIW processors
C Alippi, W Fornaciari, L Pozzi, M Sami
Proceedings of the conference on Design, automation and test in Europe, 57-es, 1999
Introduction of local memory elements in instruction set extensions
P Biswas, V Choudhary, K Atasu, L Pozzi, P Ienne, N Dutt
Proceedings of the 41st annual Design Automation Conference, 729-734, 2004
Stream computations organized for reconfigurable execution
A DeHon, Y Markovsky, E Caspi, M Chu, R Huang, S Perissakis, L Pozzi, ...
Microprocessors and Microsystems 30 (6), 334-354, 2006
Approximate logic synthesis: A survey
I Scarabottolo, G Ansaloni, GA Constantinides, L Pozzi, S Reda
Proceedings of the IEEE 108 (12), 2195-2213, 2020
Polynomial-time subgraph enumeration for automated instruction set extension
P Bonzini, L Pozzi
2007 Design, Automation & Test in Europe Conference & Exhibition, 1-6, 2007
ISEGEN: Generation of high-quality instruction set extensions by iterative improvement
P Biswas, S Banerjee, N Dutt, L Pozzi, P Ienne
Design, Automation and Test in Europe, 1246-1251, 2005
A simulation-based methodology for evaluating the DPA-resistance of cryptographic functional units with application to CMOS and MCML technologies
F Regazzoni, S Badel, T Eisenbarth, J Grobschadl, A Poschmann, ...
2007 International Conference on Embedded Computer Systems: Architectures …, 2007
Automatic identification of application-specific functional units with architecturally visible storage
P Biswas, N Dutt, P Ienne, L Pozzi
Proceedings of the Design Automation & Test in Europe Conference 1, 1-6, 2006
Lattice-traversing design space exploration for high level synthesis
L Ferretti, G Ansaloni, L Pozzi
2018 IEEE 36th International Conference on Computer Design (ICCD), 210-217, 2018
Circuit carving: A methodology for the design of approximate hardware
I Scarabottolo, G Ansaloni, L Pozzi
2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 545-550, 2018
Virtual memory window for application-specific reconfigurable coprocessors
M Vuletić, L Pozzi, P Ienne
Proceedings of the 41st annual Design Automation Conference, 948-953, 2004
Performance and energy benefits of instruction set extensions in an FPGA soft core
P Biswas, S Banerjee, N Dutt, P Ienne, L Pozzi
19th International Conference on VLSI Design held jointly with 5th …, 2006
Recurrence-aware instruction set selection for extensible embedded processors
P Bonzini, L Pozzi
IEEE transactions on very large scale integration (VLSI) systems 16 (10 …, 2008
Cluster-based heuristic for high level synthesis design space exploration
L Ferretti, G Ansaloni, L Pozzi
IEEE Transactions on Emerging Topics in Computing 9 (1), 35-43, 2018
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