Marius Minea
Marius Minea
Adresă de e-mail confirmată pe cs.upt.ro - Pagina de pornire
Titlu
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State space reduction using partial order techniques
EM Clarke, O Grumberg, M Minea, D Peled
International Journal on Software Tools for Technology Transfer 2 (3), 279-287, 1999
1921999
Static partial order reduction
R Kurshan, V Levin, M Minea, D Peled, H Yenigün
International Conference on Tools and Algorithms for the Construction and …, 1998
1321998
The AVANTSSAR platform for the automated validation of trust and security of service-oriented architectures
A Armando, W Arsac, T Avanesov, M Barletta, A Calvi, A Cappai, ...
International Conference on Tools and Algorithms for the Construction and …, 2012
1152012
Computing quantitative characteristics of finite-state real-time systems
S Campos, E Clarke, W Marrero, M Minea, H Hiraishi
RTSS, 266-270, 1994
1041994
Assume-guarantee reasoning for hierarchical hybrid systems
TA Henzinger, M Minea, V Prabhu
International Workshop on Hybrid Systems: Computation and Control, 275-290, 2001
952001
Verus: a tool for quantitative analysis of finite-state real-time systems
S Campos, E Clarke, W Marrero, M Minea
Proceedings of the ACM SIGPLAN 1995 workshop on Languages, compilers …, 1995
821995
Verifying the performance of the PCI local bus using symbolic techniques
S Campos, E Clarke, W Marrero, M Minea
Proceedings of ICCD'95 International Conference on Computer Design. VLSI in …, 1995
711995
Partial order reduction for model checking of timed automata
M Minea
International Conference on Concurrency Theory, 431-446, 1999
661999
Relooper: refactoring for loop parallelism in Java
D Dig, M Tarce, C Radoi, M Minea, R Johnson
Proceedings of the 24th ACM SIGPLAN conference companion on Object oriented …, 2009
622009
Duplicate code detection using anti-unification
P Bulychev, M Minea
Proceedings of the Spring/Summer Young Researchers’ Colloquium on Software …, 2008
532008
Synthesis of VHDL concurrent processes
P Eles, M Minea, K Kuchcinski, Z Peng
European Design Automation Conference: Proceedings of the conference on …, 1994
481994
The Verus tool: A quantitative approach to the formal verification of real-time systems
S Campos, E Clarke, M Minea
International Conference on Computer Aided Verification, 452-455, 1997
461997
Compiling VHDL into a high-level synthesis design representation.
P Eles, K Kuchcinski, Z Peng, M Minea
EURO-DAC, 604-609, 1992
391992
Combining software and hardware verification techniques
RP Kurshan, V Levin, M Minea, D Peled, H Yenigün
Formal Methods in System Design 21 (3), 251-280, 2002
382002
An evaluation of duplicate code detection using anti-unification
P Bulychev, M Minea
Proc. 3rd International Workshop on Software Clones, 2009
352009
Timing analysis of industrial real-time systems
S Campos, E Clarke, W Marrero, M Minea
Proceedings of 1995 IEEE Workshop on Industrial-Strength Formal …, 1995
351995
Partial order reduction for verification of timed systems
M Minea
CARNEGIE-MELLON UNIV PITTSBURGH PA SCHOOL OF COMPUTER SCIENCE, 1999
331999
Specifying and verifying partial order properties using template MSCs
B Genest, M Minea, A Muscholl, D Peled
International Conference on Foundations of Software Science and Computation …, 2004
322004
Equivalence checking using abstract BDDs
S Jha, Y Lu, M Minea, EM Clarke
Proceedings International Conference on Computer Design VLSI in Computers …, 1997
311997
Verifying hardware in its software context and vice-versa
RP Kurshan, V Levin, M Minea, DA Peled, H Yenigun
US Patent 6,209,120, 2001
302001
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