Anastasiia Butko, PhD.
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Accuracy evaluation of gem5 simulator system
A Butko, R Garibotti, L Ost, G Sassatelli
7th International workshop on reconfigurable and communication-centric†…, 2012
Full-system simulation of big. little multicore architecture for performance and energy exploration
A Butko, F Bruguier, A Gamatiť, G Sassatelli, D Novo, L Torres, M Robert
2016 ieee 10th international symposium on embedded multicore/many-core†…, 2016
A trace-driven approach for fast and accurate simulation of manycore architectures
A Butko, R Garibotti, L Ost, V Lapotre, A Gamatie, G Sassatelli, ...
The 20th Asia and South Pacific Design Automation Conference, 707-712, 2015
Design exploration for next generation high-performance manycore on-chip systems: Application to big. little architectures
A Butko, A Gamatiť, G Sassatelli, L Torres, M Robert
2015 IEEE Computer Society Annual Symposium on VLSI, 551-556, 2015
Understanding quantum control processor capabilities and limitations through circuit characterization
A Butko, G Michelogiannakis, S Williams, C Iancu, D Donofrio, J Shalf, ...
IEEE 2020 International Conference on Rebooting Computing (ICRC), 10, 2020
Deep learning segmentation of complex features in atomic-resolution phase-contrast transmission electron microscopy images
R Sadre, C Ophus, A Butko, GH Weber
Microscopy and microanalysis 27 (4), 804-814, 2021
Exploration of magnetic ram based memory hierarchy for multicore architecture
S Senni, L Torres, G Sassatelli, A Bukto, B Mussard
2014 IEEE Computer Society Annual Symposium on VLSI, 248-251, 2014
Efficient Programming for Multicore Processor Heterogeneity: OpenMP versus OmpSs
A Butko, F Bruguier, A Gamatiť, G Sassatelli
Open Source Supercomputing Workshop, 2017
5G enabled energy innovation: Advanced wireless networks for science (workshop report)
P Beckman, C Catlett, M Ahmed, M Alawad, L Bai, P Balaprakash, ...
Argonne National Lab.(ANL), Argonne, IL (United States); Northwestern Univ†…, 2020
Exploration of Performance and Energy Trade-offs for Heterogeneous Multicore Architectures
A Butko, F Bruguier, D Novo, A Gamatiť, S Gilles
arXiv preprint arXiv:1902.02343, 2019
Efficient embedded software migration towards clusterized distributed-memory architectures
R Garibotti, A Butko, L Ost, A Gamatiť, G Sassatelli, C Adeniyi-Jones
IEEE Transactions on Computers 65 (8), 2645-2651, 2015
Exploiting memory allocations in clusterised many‐core architectures
R Garibotti, L Ost, A Butko, R Reis, A Gamatiť, G Sassatelli
IET Computers & Digital Techniques 13 (4), 302-311, 2019
SRNoC: A statically-scheduled circuit-switched superconducting race logic NoC
G Michelogiannakis, D Lyles, P Gonzalez-Guerrero, M Bautista, ...
2021 IEEE International Parallel and Distributed Processing Symposium (IPDPS†…, 2021
Position Paper: OpenMP scheduling on ARM big. LITTLE architecture
A Butko, L Bessad, D Novo, F Bruguier, A Gamatiť, G Sassatelli, L Torres, ...
9th Int’l Workshop on Programmability and Architectures for Heterogeneous†…, 2016
Towards an Integrated Strategy to Preserve Digital Computing Performance Scaling Using Emerging Technologies
D Vasudevan, A Butko, G Michelogiannakis, D Donofrio, J Shalf
Workshop on HPC computing in a Post Moore’s law world (HCPM), 2017
Power efficient thermally assisted switching magnetic memory based memory systems
S Senni, L Torres, G Sassatelli, A Butko, B Mussard
Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2014 9th†…, 2014
Open2C: Open-source generator for exploration of coherent cache memory subsystems
A Butko, A Chen, D Donofrio, F Fatollahi-Fard, J Shalf
Proceedings of the International Symposium on Memory Systems, 311-317, 2018
Towards automated superconducting circuit calibration using deep reinforcement learning
MG Bautista, ZJ Yao, A Butko, M Kiran, M Metcalf
2021 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 462-467, 2021
Real-time Fast Feedback Experiment enabled by a Customized FPGA-Based Control System
A Butko, Y Xu, G Huang, R Naik, D Santiago, I Siddiqi
Bulletin of the American Physical Society, 2023
TIGER: Topology-aware Assignment using Ising machines Application to Classical Algorithm Tasks and Quantum Circuit Gates
A Butko, I Turimbetov, G Michelogiannakis, D Donofrio, D Unat, J Shalf
arXiv preprint arXiv:2009.10151, 2020
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