Urmăriți
Maciej Ciesielski
Maciej Ciesielski
Professor of ELectrical and Computer Engineering
Adresă de e-mail confirmată pe ecs.umass.edu
Titlu
Citat de
Citat de
Anul
BDS: A BDD-based logic optimization system
C Yang, M Ciesielski, V Singhal
Proceedings of the 37th Annual Design Automation Conference, 92-97, 2000
3472000
Wave-pipelining: a tutorial and research survey
WP Burleson, M Ciesielski, F Klass, W Liu
IEEE Transactions on very large scale integration (vlsi) systems 6 (3), 464-474, 1998
3401998
Logic synthesis and verification
S Hassoun, T Sasao
Springer Science & Business Media, 2001
2212001
Optimum and suboptimum algorithms for input encoding and its relationship to logic minimization
S Yang, MJ Ciesielski
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions …, 1991
1291991
LPSAT: a unified approach to RTL satisfiability
Z Zeng, P Kalla, M Ciesielski
Proceedings Design, Automation and Test in Europe. Conference and Exhibition …, 2001
1182001
Taylor expansion diagrams: A canonical representation for verification of data flow designs
M Ciesielski, P Kalla, S Askar
IEEE Transactions on Computers 55 (9), 1188-1201, 2006
872006
Verification of gate-level arithmetic circuits by function extraction
M Ciesielski, C Yu, W Brown, D Liu, A Rossi
Proceedings of the 52nd Annual Design Automation Conference, 1-6, 2015
852015
Taylor expansion diagrams: A compact, canonical representation with applications to symbolic verification
MJ Ciesielski, P Kalla, Z Zheng, B Rouzeyre
Proceedings 2002 Design, Automation and Test in Europe Conference and …, 2002
852002
Incremental SAT-based reverse engineering of camouflaged logic circuits
C Yu, X Zhang, D Liu, M Ciesielski, D Holcomb
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017
822017
PLADE: A two-stage PLA decomposition
MJ Ciesielski, S Yang
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions …, 1992
731992
Expression of HER2 in colorectal cancer does not correlate with prognosis
WJ Kruszewski, R Rzepko, M Ciesielski, J Szefel, J Zieliński, M Szajewski, ...
Disease markers 29 (5), 207-212, 2010
682010
Formal verification of arithmetic circuits by function extraction
C Yu, W Brown, D Liu, A Rossi, M Ciesielski
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2016
672016
Fast algebraic rewriting based on and-inverter graphs
C Yu, M Ciesielski, A Mishchenko
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2017
642017
Clock period minimization with wave pipelining
DA Joy, MJ Ciesielski
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 1993
561993
BDD decomposition for efficient logic synthesis
C Yang, V Singhal, M Ciesielski
Proceedings 1999 IEEE International Conference on Computer Design: VLSI in …, 1999
531999
An optimum layer assignment for routing in ICs and PCBs
MJ Ciesielski, E Kinnen
18th Design Automation Conference, 733-737, 1981
511981
Understanding algebraic rewriting for arithmetic circuit verification: a bit-flow model
M Ciesielski, T Su, A Yasin, C Yu
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2019
492019
Multiple-valued Boolean minimization based on graph coloring
MJ Ciesielski, S Yang, MA Perkowski
Proceedings 1989 IEEE International Conference on Computer Design: VLSI in …, 1989
491989
Functional test generation using constraint logic programming
Z Zeng, MJ Ciesielski, B Rouzeyre
11th International Conference on VLSI/SOC, 375-387, 2002
462002
Practical design verification
DK Pradhan, IG Harris
Cambridge University Press, 2009
382009
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